VLSI Implementation of High Speed DCT Architecture for H.264 Video Codec Design

Field programmable gate arrays are ideally suited for the implementation of DCT based digital image compression. However, there are several issues that need to be solved. The Multiply-Accumulate Unit (MAC) is the main computational kernel in DIP architectures. The MAC unit establishes the power and the speed of the overall system; it always lies in the critical path. To develop high speed and low power MAC is crucial to use DSP in the future wireless sensor networks. In this work, a fast and low power MAC Unit is proposed for 2D-DCT computation. The proposed architecture is based on modified booth radix-8 with merged MAC architectures to design a unit with a low critical path delay and low hardware complexity. This new architecture reduces the hardware complexity of the summation network to reduce the overall power and area. Increasing the speed of operation is achieved by feeding the bits of the accumulated operand into the summation tree before the final adder instead of going through the entire summation network. The FPGA implementation of the proposed booth radix-8 based MAC unit saves 64% of the area, to the regular merged MAC unit with conventional multiplier.